-,--" .>.".- 8 ,. analog w devices high performance analog to digital converter adc1133 features 12 bit resolution very small module package no missing codes: 0 to +70c 25,us conversion time programmable input ranges 8 general description the adcl133 is a high perfonnance, 12-bit aid converter packaged in an exceptionally compact 2" x 2" x 0.4" (51 x 51 x 10mm) module. using the successive approxima- tions technique, it perfonns complete conversions in less than 25,us. perfonnance specifications include :t7.5ppm/oc gain temperature coefficient, :tlhlsb linearity error and no missing codes from 0 to +70oc. the adcl133 combines the ad562 integrated circuit d/a with a precision reference source, a high speed comparator, and successive approximations logic to fond a complete con- verter package. the laser trimmed ad562, which consists of precision current switches and a very stable thin film resistor network, provides the adc 1133 with very good perfonnance over temperature and makes possible its small module size. timing as shown in figure 1, the "0" to "1" transition of the con- vert command input sets the msb output to logic "0" and the clock, status, msb, and bit 2 through bit 12 out- puts to logic "1". nothing further happens until the convert command returns to logic "0", at which time the conversion proceeds. with the msb in the logic "0" state, the internal digital-to- analog converter's output is compared with the analog input. if the d/a output is less than the analog input, the first "0" to "1" clock transition resets the msb to logic "1". ifthe d/a output is greater than the analog input, the msb re- mains at logic "0". 8 information furnished by analog devices is believed to be accurate and reliable, however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implica- tion or otherwise under any patent or patent rights of analog devices. the first "0" to "1" clock transition also sets the bit 2 out- put to logic "0" and another comparison is made. this pro- cess continues through each successive bit until the bit 12 (lsb) comparison is completed. at this time the status output returns to logic "0" and the conversion cycle ends. the serial data output is of the non-return-to-zero (nrz) type. the data is available, msb first, 40ns after each of the twelve "0" to "1" clock transitions. gg~~~~~ ii clock l- status j msb 1 bit 2 bit3 u bit 11 lsb ~ msiij bit 2 bit 11 serial ~,.,..".,...,...,.~ output msb bit 3 lsb previous word: 111...11 new word: 101 . . ,01 figure 1. timing diagram route 1 industrial park; p.o. box 280; norwood, mass. 02062 tel: 617/329-4700 twx: 710/394-6577 west coast mid-west texas 213/595.1783 312/894.3300 214/231-5094 obsolete
-,.""",--, specifica tions (typical @ +25c and :t 15v unless otherwise noted) resolution conversion time! accuracy2 error relative to full scale quantization error differential nonlinearity error temperature coefficients gain offset (unipolar inputs) offset (bipolar inputs) differential nonlinearity missing codes input voltage ranges input impedance t5v,o to +iov range :!:lov range convert command 12 bits 251!s max t'hlsb max t'hlsb max t'hlsb (tilsb max) t7.5ppm/oc (ti5ppm/c max) t25jj.v/c (t40jj.v/c max) t25jj.v/c (t40jj.v/oc max) t2.8ppm/c (t3ppm/oc max) no missing codes 0 to +70c t5v, tiov, 0 to +iov sku loku positive pulse, ttl compatible loons min width parallel data output unipolar inputs bipolar inputs positive true binary positive true offset binary or two's complement serial data output unipolar inputs bipolar inputs status output clock output logic fanouts and loading convert command parallel data outputs starus output status output serial data output clock output adjustment ranges gain offset power requirements positive true binary positive true offset binary, ttl com- patible, nrz format, msb first logic "i" during conversion ttl compatible 480khz, ttl compatible i ttl load 6ttl loads/bit 4ttl loads 10ttl loads 6ttl loads 9ttl loads t5lsb min tiolsb min +5vdc t5% @ 120ma (l60ma max) +15vdc t3%@ 15ma (20ma max) -15vdc t3% @ 25ma (30ma max) power supply sensitivity3 gain offset reference t1.5mv/v t1.5mv/v to.5mv/v temperature range operating storage price (1-9) 0 to +70oc -ssoc to +85c rnv 1 conversion time is measured from the trailing edge of the convert command to the "i" to "0" transition of the status output. , warmup time to rated accuracy is 5 minutes. . specification applies only when tracking + 15v and -15v supplies are used, and for slowly occuring variations in power supply voltages. specifications subject to change without notice. -2- outline dimensions dimensions shown in inches and (mm). i-- ~5~wax ~ 15 -j ~~ '41 max (10.4) 0.2min (5.1) . ~ 1 2.01 max (51.1) 1 bottom view 0.112.51 grid -i r- pins are half hard brass, gold plated per mil-g-45204b, class i, type ii. pin diameter is 0.019" (o.483mm) to.001" (0.025mm). for plug-in mounting card, order board no. ac1505 @ $30. block diagram and pin designations 28 27 26 25 digital to analog converter 24 23 22 successive approximation logic 21 20 19 18 17 16 15 ia ref. out 1 offset adjust 2 +i5v 3 -isv 4 gain adj. ship. offset 6 10v input 7 20v input 8 analog gnd. 9 +sv 10 cony. comm. 11 status 12 status 13 clock out 14 digital gnd. 8 1a 1 2 3 4 9 10 11 12 13 14 15 serial out 16 bit 12 (lsb) 17 bit 11 18 bit 10 19 bit 9 20 bit 8 21 bit 7 22 bit 6 23 bit 5 24 bit 4 2s bit 3 26 bit 2 27 bit 1 (msb) 28 msb 8 -- obsolete
applying the adc1133. 8 module connections figure 2 shows the connections required to operate the adcl133 with a :t10v input range (except for connections to the bit and status digital outputs, which are obvious). this figure also shows the power supply bypass capacitors that are recommended on page 4. """"15turn offset aojust this jumper isoeleteo when operation on the a to .lav range is oesireo. loon. 15 turn ( gain adjust .15v .15v l ia 1 , 3 ,'av"analog input ~ " .5v convert commano input 8 figure 2. module connections the adcl133 can be operated with an input range of :tsv by connecting the analog input to pin 6 instead of pin 7. opera- tion on the 0 to + 1 ov range is achieved by deleting the jumper between pins 1a and s, and connecting the analog input to pin 6. if an input impedance of greater than skn on the :!:sv or 0 to + 10v ranges, or 10kn on'the :t10v range is desired, an opera- tional amplifier input buffer will be required. the analog devices ads09 fast settling integrated circuit differential amplifier would be an ideal choice. parallel data output the adcl13 3 produces natural binary coded outputs when configured as a unipolar device; as a bipolar device it can produce either offset binary or two's complement output codes. the most significant bit is represented by pin 27 (the msb output) for binary and offset binary codes and by the pin 28 (the msb output) for the two's complement code. tables i and ii below illustrate the relationship between the analog input and digital output for all three codes. analog input digital output binary code +9.9976v +s .oooov +1.2s00v +o.0024v +o.oooov 111111111111 100000000000 001000000000 000000000001 000000000000 table i. nominal unipolar input-output relationships 8 the user should note that under worst case conditions, the lsb output will not be valid until 28ns after the "i" to "0" transition of the status output. if this is not properly accounted for in the design of the external digital circuitry, the lsb might always appear as a "0" to the system. - table ii. nominal bipolar input-output relationships gain and offset adjustments the adcl133 is calibrated with external gain and offset adjust- ment potentiometers connected as shown in figure 2. the off- set adjustment potentiometer has an adjustment range of at least :t10lsb's, and the gain range adjustment potentiometer has an adjustment range of at least :tslsb's. offset calibration is not affected by changes in gain calibration, and should therefore be performed prior to gain calibration. proper gain and offset calibration requires great care and the use of extremely sensitive and accurate reference instruments. the voltage standard used as a signal source must be very stable. it should be capable of being set to within :tl/10lsb of the desired value at any point within its range. these adjustments are not made with zero and full scale input signals, and it may be helpful to understand why. an aid con- verter will produce a given digital word output for a small range of input signals, the nominal width of the range being one lsb. if the input test signal is set to a value which should cause the converter to be on the verge of switching between two adjacent digital outputs, the unit can be calibrated so that it does switch at just that point. with a high speed convert command rate and a visual display, these adjustments can be performed in a very accurate and sensitive way. analog devices' conver- sion handbook gives more detailed information on testing and calibrating aid converters. offset calibration for unipolar units set the input voltage precisely to +0.0012v and adjust the offset potentiometer until the converter is just on the verge of switching from 000000000000 to 000000000001. for :!:sv bipolar units set the input voltage precisely to -4.9988v; for :!:10v units set it to -9.9976v. adjust the off- set potentiometer until offset binary coded units are just on the verge of switching from 000000000000 to 000000000001 and two's complement coded units are just on the verge of switching 100000000000 to 100000000001. gain calibration set the input voltage precisely to +9.9963v for unipolar units, +4.9963v for :tsv units, 6r +9.9926v for :t10v units. note that these values are 1lhlsb's less than nominal full scale. adjust the loon variable gain resistor until binary and off- set binary coded units are just on the verge of switching from 111111111110 to 111111111111 and two's complement coded units are just on the verge of switching from 011111111110 to 011111111111. -3- analog input i digital output two's :tsv :t10v offset binary complement range range code code +4.9976v +9.99s1v 111111111111 011111111111 +2.s000v +s.oooov 110000000000 010000000000 +0.0024v +0.0049v 100000000001 000000000001 +o.oooov +o.oooov 100000000000 000000000000 -s .oooov -10.0000v 000000000000 100000000000 obsolete
power supply and grounding connections the adcl133 requires power supplies of +15v, -15v, and +5v which are connected to pins 2,3, and 9 respectively. the +5v power supply return and digital return are connected to digit al ground (pin 14) while the :!:15v supply return and analog signal return are connected to analog ground (pin 8). the analog and digital grounds are not connected within the module but it is recommended that they be tied together externally with a short jumper between the two pins. if this is done, care must be taken to assure that no digital sig- ilals are present on the analog ground return. the +5v and :!:15v supplies are internally bypassed, but it is recommended that additional bypass capacitors be added ex- ternally. the capacitors should be located as near to the module pins as possible. the +5v bypass capacitor should be connected between the +5v input (pin 9) and digital ground (pin 14). the :!:15v bypass capacitors should be connected between pin 2 and analog ground (pin 8), and between pin 3 and analog ground. the capacitors would typically be 10j,lf (or greater) tantalum types. serial data output the serial data output, available on pin 15, is of the non-return- to-zero format. the data is transmitted msb first and is binary coded for unipolar units and offset binary coded for bi- polar units. figure 3, shown below, indicates one method for transmitting data serially using only three wires (plus a digital ground). the data is clocked into a receiving shift register using the delayed clock output of the adcl133. . lsb status serial out figure 3. serial data transmission the timing diagram presented in figure 4 shows that the con- verter's clock output must be delayed by an amount of time greater than or equal to the sum of the receiving shift register setup time plus the 40ns maximum clock output to serial output delay. clock output first clock second clock third clock i pulse i pulse pulse " 'i' ,', ,i i i i serial data output i-: i, 'i .' 800ns i 11'5 i i -jf msb = 1 \ bit 2 = 0 ii --i r-- 40ns (max) i i i --'i 'i -->1 r- receiving shift register setup time / shift register strobe figure 4. serial data timing diagram the data appearing in the shift register will be valid a period of time equal to the shift register propagation delay, after the "0" to "i" transition of the last shift register strobe pulse. repetitive conversions when making repetitive conversions in the parallel output mode, at least loons must be allowed between the comple- tion of one conversion and the beginning of the next. this results in a throughput rate of 39.7khz. when operating in the serial output mode, an additional period qf time may be necessary to assure that the data from one conversion has been completely entered in the receiving shift register before the next conversion is initiated. the ac1505 mounting card the ac1505 mounting card is available to assist in the applica- tion of the adcl133. this 4.5" x 3.0" printed circuit card, shown below in figure 5, has sockets which allow an adcl133 to be plugged directly onto it. it includes the necessary gain and offset adjustment potentiometers and power supply by- pass capacitors. it mates with a cinch 251-22-30-160 (or equivalent) edge connector which is supplied with every card. jumpers can be installed on the printed circuit card to pro- gram the analog input range. r i 4.500 (114.301 dimensions shown are in inches and (mm). ~~ msb 3.000 (76.20) adc1133 figure 5. ac7505 outline drawing -4- . it) i' ~ 0 i' m m m u j 8 ~ en ::i z 0 w i- z a: c.. 8 obsolete
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